Leading edge consumer electronic products demand innovative and cost-effective packaging solutions. While front end silicon technologies have followed Moore's law by device scaling, the back end infrastructure has lagged in similar advancements. This has created an interconnect gap whereby the signal speed achieved on the silicon side is significantly higher than the speed achieved on the printed circuit boards. To this end, innovative advancements in the back-end processing, such as fan-out wafer level packaging technology, have been developed that deliver robust packaging solutions to meet the performance and reliability requirements for leading edge devices such as wireless chips.
Fan-out wafer level packaging technology addresses the pad limitations associated with conventional wafer level packaging techniques and has miniaturization and potential low cost packaging advantages. It also enables high-performance bump interconnects with input/output (I/O) counts exceeding the capacity of the original front-end chip size. The bump array area for each chip is increased by populating a composite wafer with tested “known good” chips at a larger repeat pitch than the original wafer. The reconstituted wafer preferably has the size and shape of a standard silicon wafer, thereby allowing the use of existing wafer processing equipment for subsequent handling and processing. For compatibility with planar processing steps, the chip surface needs to be coplanar with the wafer molding compound. Also the X, Y, and θ positioning of each chip needs to be accurate within the grid to maintain registration performance while patterning multiple chips per exposure.
Chip positioning control within a reconstituted wafer is one of the key factors affecting the downstream process requirements. While considerable improvements have been made with the chip pick and place equipment, it is difficult to control the shift of the silicon chip during the compression molding process. This creates significant alignment challenges during the subsequent photolithography process steps.